Tag: Circuit

Two Trump-appointed circuit judges don’t think much of shareholder class actions

(Reuters) – Last week, a three-judge panel of the 9th U.S. Circuit Court of Appeals issued a significant decision in a shareholder class action against BofI, a bank holding company. The appeals court, in an opinion by Judge Paul Watford, revived a class action alleging, among other things, that the bank’s share price plunged in response to disclosures in a whistleblower lawsuit. The 9th Circuit joined the 6th Circuit to conclude that a whistleblower complaint containing allegations from a corporate insider can serve as a “corrective disclosure” of the company’s misstatements. If the market perceives the whistleblower’s allegations to be true and reacts accordingly, the appeals court held, shareholders can base their loss causation arguments on the filing of the lawsuit.

Judge Kenneth Lee, who was nominated to the 9th Circuit by President Donald Trump and assumed office in 2019, dissented from that part of the 9th Circuit

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Innovative Strategies Are Improving Early Design Circuit Verification

Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, where various blocks are implemented in parallel with the full-chip design. These blocks, which consist of both internal and 3rd-party supplier intellectual property (IP), are frequently in different stages of completion during the verification cycle, as shown in figure 1.


Fig. 1: Parallel design flows often contain blocks in different stages of completion.

However, design teams typically can’t wait to run LVS verification until all the blocks are complete and implemented, for several reasons:

  • Merging completed blocks can result in numerous connectivity errors between the blocks
  • There is less time to debug errors
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