Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and complex foundry decks, meeting planned tapeout deadlines in the quickest turnaround time (TAT) can be difficult. In an effort to minimize TAT, most design teams now use parallelized design flows, where various blocks are implemented in parallel with the full-chip design. These blocks, which consist of both internal and 3rd-party supplier intellectual property (IP), are frequently in different stages of completion during the verification cycle, as shown in figure 1.
Fig. 1: Parallel design flows often contain blocks in different stages of completion.
However, design teams typically can’t wait to run LVS verification until all the blocks are complete and implemented, for several reasons:
- Merging completed blocks can result in numerous connectivity errors between the blocks
- There is less time to debug errors